1. Field of the Invention
Generally, the subject matter disclosed herein relates to the manufacturing of integrated circuits, and, more particularly, to advanced etch processes for patterning substantially homogeneous materials to a target depth, such as advanced trench etch processes in the dual in-laid technique and the like.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and power consumption. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of transistor elements, the available floor space for the various components, such as drain and source regions, gate electrodes of transistors and interconnect lines electrically connecting the individual circuit elements, is also decreased. Consequently, the dimensions of these components have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per chip. One prominent example in this respect are metal lines and vias provided in the wiring levels of integrated circuits. In integrated circuits having minimum dimensions of approximately 0.35 μm and less, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the involved transistor elements. As the channel length of these elements has reached 0.18 μm and less, it turns out, however, that the signal propagation delay is no longer limited by the field effect transistors but is limited, owing to the increased circuit density, by the close proximity of the metal lines in the wiring levels, since the line-to-line capacitance is increased in combination with a reduced conductivity of the lines due to a reduced cross-sectional area. The parasitic RC (resistance/capacitance) time constants therefore may require the introduction of a new type of dielectric material, preferably in combination with a highly conductive metal.
Traditionally, metallization layers are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride, with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities, in highly sophisticated integrated circuits, aluminum is commonly replaced by copper, having a significantly lower electrical resistance and a higher resistivity against electromigration. Moreover, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>5) are increasingly replaced by low-k materials to reduce the parasitic capacitance. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a low-k dielectric/copper metallization layer is associated with a plurality of issues to be dealt with.
For example, copper may not be deposited in higher amounts in an efficient manner by well-established deposition methods, such as chemical and physical vapor deposition. Moreover, copper may not be efficiently patterned by well-established anisotropic etch processes. Consequently the so-called in-laid or damascene technique is employed in forming metallization layers including copper-containing lines. Typically, in the damascene technique, the dielectric layer is deposited and then patterned with trenches and vias that are subsequently filled with a metal by plating methods, such as electroplating or electroless plating. For forming vias providing electrical connection from an overlying metal line to an underlying metal line of a lower metallization layer, the vias and the trenches may be filled in a single process so that the via and the trench have to be patterned prior to filling in the copper. A corresponding technique, also referred to as dual damascene technique, is carried out for a conventional dielectric layer stack by providing a silicon dioxide layer and an intermediate silicon nitride layer that acts as an etch stop layer for the trench etch and a second silicon dioxide layer formed thereon. Prior to or after the trench etch process, a via may be etched in the lower silicon layer, depending on the specific process strategy. In any case, the trench etch process may be reliably controlled on the basis of the intermediate etch stop layer.
When replacing the high-k material silicon dioxide by a low-k material, the situation in forming the via and trench is quite different, as the provision of an intermediate etch stop layer, such as the silicon nitride layer exhibiting a high k value, may unduly increase the permittivity of the entire dielectric layer stack. To obtain a minimum permittivity, the intermediate etch stop layer is commonly omitted. Consequently, the trench etch process may not be stopped by an intermediate etch stop layer, as typically materials having a high etch selectivity with respect to the low-k dielectric under consideration may not provide the desired low permittivity characteristics.
With reference to FIGS. 1a-1c, the situation of a trench etch process performed in a substantially homogeneous dielectric layer will be described in more detail. FIG. 1a schematically illustrates cross-sectional views of a semiconductor device 100 comprising a metallization layer 150 after the trench etch process. The semiconductor device 100 may comprise a substrate 101 in and over which may be provided circuit elements (not shown), such as transistors and the like, which are electrically connected by one or more of the metallization layers 150. The substrate 101 may further comprise an etch stop layer 102, which may be formed of any appropriate material that exhibits desired characteristics with respect to covering any buried regions, such as metal regions and the like, and to serve as an etch stop layer during a via etch process for forming a via 151 in a dielectric material layer 152 of the metallization layer 150. The dielectric layer 152 may be provided, at least over an extended height, as a substantially homogeneous material, such as a low-k material, in order to obtain a low overall permittivity. Furthermore, a trench 153 is formed in an upper portion of the layer 152, wherein the trench 153 may have a depth 153D that, in combination with the respective trench width, is an important factor for determining the characteristics of the metallization layer 150 with respect to reliability. That is, the conductivity, the electromigration behavior and the like may be influenced by the thickness of the respective metal lines formed from the trench 153. Thus, the depth 153D may represent an important design measure for adjusting the operational behavior of the semiconductor device 100.
A typical process flow for forming the device 100 as shown in FIG. 1a may comprise the following processes. After any circuit elements have been formed in and above the substrate 101, the etch stop layer 102 may be deposited by any appropriate deposition technique, such as chemical vapor deposition (CVD), spin-on techniques and the like. Thereafter, the dielectric layer 152 may be formed using any manufacturing technique as appropriate in view of material and process requirements. Next, an etch process may be performed, wherein, depending on the process requirements, the via 151 may be formed first on the basis of an appropriate patterning regime. Subsequently, the trench 153 may be formed, wherein the surface topography may be suitably planarized prior to performing a corresponding patterning process for forming an etch mask for the trench 153. Thereafter, an etch process is performed on the basis of a specified set of process parameters. Due to the homogeneous nature of the layer 152, the depth 153D may be controlled by adjusting the etch time.
As is well-known, in complex manufacturing environments, a plurality of etch chambers may be used for the various etch processes, wherein process fluctuations may occur, which may, however, directly translate into respective depth fluctuations during the trench etch process. Moreover, even within a single etch chamber, the etch rate may vary slightly, even if the respective process parameters are maintained at their target values. Consequently, an unwanted depth fluctuation may be observed between substrates or lots of substrates after the trench etch process.
FIG. 1b schematically illustrates the device 100 formed on a different substrate, wherein the respective trench 153 has a depth 153A that is greater than the target value 153D. FIG. 1c schematically shows the device 100 formed above yet another substrate. In this case, the respective trench 153 may have a depth 153B that is less than the target value 153D.
Consequently, the devices 100 according to FIG. 1a-1c at least may have a significantly differing operational behavior, wherein a certain degree of fluctuation may even result in faulty devices.
It has therefore been proposed to introduce a material into the layer 152, which may have different characteristics during an optical endpoint detection, while not unduly affecting the overall permittivity of layer 152. Since a corresponding intermediate layer may be deposited during the formation of the layer 152 with a reduced degree of process non-uniformity compared to the etch fluctuations described above, thereby allowing, in principle, an enhanced detectability of the end of the trench etch process, the high degree of similarity of the etch indicator material compared to the actual material of the layer 152, required for maintaining the overall permittivity at a low level, may raise significant difficulties in detecting the intermediate etch indicator layer when the etch front releases respective atomic species into the etch ambient. Thus, the resulting optical endpoint signal may not be reliable.
In view of the situation described above, there exists a need for a technique that enables the formation of trenches in materials in a more reliable manner, while avoiding or at least reducing the effects of one or more of the problems identified above.